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| author | ducky | 2017-02-01 16:07:09 -0800 |
|---|---|---|
| committer | Richard Lin | 2017-02-07 16:24:17 -0800 |
| commit | 8d2fff4eff3ba0f92437b290985b35afbb0ed565 (patch) | |
| tree | 97b3f62d73c61ceb12ccb6bd684e63df5be8ed0d /src/main/scala/chisel3/util/LFSR.scala | |
| parent | ad20406f301e04075e051147092cf9c12a6a6ca8 (diff) | |
Name all the things
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index 83dc907d..94c340c4 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -6,6 +6,7 @@ package chisel3.util import chisel3._ +import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order //import chisel3.core.ExplicitCompileOptions.Strict // scalastyle:off magic.number @@ -15,6 +16,7 @@ object LFSR16 { * * @param increment optional control to gate when the LFSR updates. */ + @chiselName def apply(increment: Bool = true.B): UInt = { val width = 16 val lfsr = Reg(init=1.U(width.W)) |