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| author | Jim Lawson | 2016-08-22 16:57:43 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-22 16:57:43 -0700 |
| commit | 35c8e40b25f529da883e8ae91644fcc496e087da (patch) | |
| tree | ce778a20c0a05848e5578a1d514e7049e98a23c4 /src/main/scala/chisel3/util/Decoupled.scala | |
| parent | 94796f5960b5b82f9d28d2b0e0e7ec7c92e29dfa (diff) | |
Purely cosmetic changes to placate the scalastyle checker.
Diffstat (limited to 'src/main/scala/chisel3/util/Decoupled.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 0d000f49..42f58ea9 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -103,7 +103,7 @@ class Queue[T <: Data](gen: T, val entries: Int, extends Module(override_reset=override_reset) { def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = this(gen, entries, pipe, flow, Some(_reset)) - + val io = IO(new QueueIO(gen, entries)) val ram = Mem(entries, gen) |