diff options
| author | Jim Lawson | 2016-07-20 17:08:55 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 17:08:55 -0700 |
| commit | 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 (patch) | |
| tree | 1cea032150aae31fdf7cb995b26724be4b0ceb38 /src/main/scala/chisel3/util/Decoupled.scala | |
| parent | 2dce378deda1cc33833eb378c89a1c5415817bae (diff) | |
More literal/width rangling.
Diffstat (limited to 'src/main/scala/chisel3/util/Decoupled.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 5958c744..037f9a22 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -82,7 +82,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ val deq = DeqIO(gen) /** The current amount of data in the queue */ - val count = Output(UInt(log2Up(entries + 1))) + val count = Output(UInt.width(log2Up(entries + 1))) } /** A hardware module implementing a Queue |