Merge branch 'master' into exceptionfix

1 files changed, 4 insertions, 4 deletions

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index d478e10e..a422b5fe 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,15 +10,15 @@ import chisel3._
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt(0)
+      0.U
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
@@ -30,7 +30,7 @@ object Log2 {
 
   /** Returns the base-2 integer logarithm of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits): UInt = apply(x, x.getWidth)