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| author | Jim Lawson | 2016-08-18 12:35:34 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-18 12:35:34 -0700 |
| commit | d18274e307271809db2c27676f1dca40a49c9627 (patch) | |
| tree | 2632a0e409bea3f9069c5ebfb555cc1ec04caa4f /src/main/scala/chisel3/util/CircuitMath.scala | |
| parent | ddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff) | |
| parent | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (diff) | |
Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests
Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
Diffstat (limited to 'src/main/scala/chisel3/util/CircuitMath.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/CircuitMath.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index a64447d9..c809e14b 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -10,7 +10,7 @@ import chisel3._ /** Compute the base-2 integer logarithm of a UInt * @example * {{{ data_out := Log2(data_in) }}} - * @note The result is truncated, so e.g. Log2(UInt(13)) = 3 + * @note The result is truncated, so e.g. Log2(13.U) = 3 */ object Log2 { /** Compute the Log2 on the least significant n bits of x */ |