diff options
| author | Andrew Waterman | 2016-07-07 00:11:15 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-07-07 00:34:03 -0700 |
| commit | fb39f7dc372b5836f02d8d7964f5fcc6a38f8747 (patch) | |
| tree | ca446855b34936b45692657dd8255d2a616c34ac /src/main/scala/chisel3/util/Bitwise.scala | |
| parent | 378edecbf797f19cf26f5a4d6a3ed3df701ba66d (diff) | |
Avoid needlessly creating Vecs
Diffstat (limited to 'src/main/scala/chisel3/util/Bitwise.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Bitwise.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index ab1ff550..7f295200 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -11,7 +11,7 @@ import chisel3.core.SeqUtils object FillInterleaved { def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) - def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits + def apply(n: Int, in: Seq[Bool]): UInt = Cat(in.map(Fill(n, _)).reverse) } /** Returns the number of bits set (i.e value is 1) in the input signal. |