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authorJim Lawson2016-08-16 11:08:32 -0700
committerJim Lawson2016-08-16 11:08:32 -0700
commita264157a47f56216cebf2d98c1c8118c344dad5f (patch)
tree1724fe2900ce336822e73f9cae8280b8474f62ab /src/main/scala/chisel3/util/Bitwise.scala
parent4ab2aa0e9209000fb0ba1299ac18db2e033f708f (diff)
parentddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff)
Merge branch 'master' into sdtwigg_connectwrap_renamechisel3
Diffstat (limited to 'src/main/scala/chisel3/util/Bitwise.scala')
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 2743e59f..1d48ec0a 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -29,7 +29,7 @@ object Fill {
n match {
case 0 => UInt.width(0)
case 1 => x
- case _ if x.widthKnown && x.getWidth == 1 =>
+ case _ if x.isWidthKnown && x.getWidth == 1 =>
Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
case _ if n > 1 =>
val p2 = Array.ofDim[UInt](log2Up(n + 1))