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authorJim Lawson2016-08-16 11:08:32 -0700
committerJim Lawson2016-08-16 11:08:32 -0700
commita264157a47f56216cebf2d98c1c8118c344dad5f (patch)
tree1724fe2900ce336822e73f9cae8280b8474f62ab /src/main/scala/chisel3/util/BitPat.scala
parent4ab2aa0e9209000fb0ba1299ac18db2e033f708f (diff)
parentddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff)
Merge branch 'master' into sdtwigg_connectwrap_renamechisel3
Diffstat (limited to 'src/main/scala/chisel3/util/BitPat.scala')
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 5b37bd1b..e79b882b 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -68,7 +68,7 @@ object BitPat {
*/
def apply(x: UInt): BitPat = {
require(x.isLit)
- val len = if (x.widthKnown) x.getWidth else 0
+ val len = if (x.isWidthKnown) x.getWidth else 0
apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
}
}