diff options
| author | Andrew Waterman | 2017-02-24 00:12:19 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 9734a42a03036e0ce329bb507b581633e86e9693 (patch) | |
| tree | ec9ed07713bcc274d5e41f61166d6025e0adf6bc /src/main/scala/chisel3/util/Arbiter.scala | |
| parent | 9cad9ec21ac7a9a8c463e2c694b6285269982a84 (diff) | |
Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0
Both should be zero-width wires.
Diffstat (limited to 'src/main/scala/chisel3/util/Arbiter.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index bbd8dd33..d2b29bf9 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -19,7 +19,7 @@ import chisel3.core.ExplicitCompileOptions.NotStrict class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { val in = Flipped(Vec(n, Decoupled(gen))) val out = Decoupled(gen) - val chosen = Output(UInt(log2Up(n).W)) + val chosen = Output(UInt(log2Ceil(n).W)) } /** Arbiter Control determining which producer has access |