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authorducky2017-02-01 16:07:09 -0800
committerRichard Lin2017-02-07 16:24:17 -0800
commit8d2fff4eff3ba0f92437b290985b35afbb0ed565 (patch)
tree97b3f62d73c61ceb12ccb6bd684e63df5be8ed0d /src/main/scala/chisel3/util/Arbiter.scala
parentad20406f301e04075e051147092cf9c12a6a6ca8 (diff)
Name all the things
Diffstat (limited to 'src/main/scala/chisel3/util/Arbiter.scala')
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 7e049c95..bbd8dd33 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -6,6 +6,7 @@
package chisel3.util
import chisel3._
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
// TODO: remove this once we have CompileOptions threaded through the macro system.
import chisel3.core.ExplicitCompileOptions.NotStrict
@@ -97,6 +98,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T
* consumer.io.in <> arb.io.out
* }}}
*/
+@chiselName
class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
/** Hardware module that is used to sequence n producers into 1 consumer.
@@ -109,6 +111,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
* consumer.io.in <> arb.io.out
* }}}
*/
+@chiselName
class Arbiter[T <: Data](gen: T, n: Int) extends Module {
val io = IO(new ArbiterIO(gen, n))