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| author | Jim Lawson | 2016-08-18 12:35:34 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-18 12:35:34 -0700 |
| commit | d18274e307271809db2c27676f1dca40a49c9627 (patch) | |
| tree | 2632a0e409bea3f9069c5ebfb555cc1ec04caa4f /src/main/scala/chisel3/testers | |
| parent | ddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff) | |
| parent | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (diff) | |
Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests
Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
Diffstat (limited to 'src/main/scala/chisel3/testers')
| -rw-r--r-- | src/main/scala/chisel3/testers/BasicTester.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index f91536d5..329237c6 100644 --- a/src/main/scala/chisel3/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -12,7 +12,7 @@ import internal.sourceinfo.SourceInfo class BasicTester extends Module { // The testbench has no IOs, rather it should communicate using printf, assert, and stop. - val io = new Bundle() + val io = IO(new Bundle()) def popCount(n: Long): Int = n.toBinaryString.count(_=='1') |