BoringUtils / Synthesizable Cross Module References (#718)

This adds an annotator that provides a linkage to the FIRRTL
WiringTransform. This enables synthesizable cross module references
between one source and multiple sinks without changing IO (the
WiringTransform bores through the hierarchy).

Per WiringTransform, this will connect sources to their closest
sinks (as determined by BFS) or fail if ownership is indeterminate.

Make TesterDriver.execute work like Driver.execute:
  - annotations are included when running FIRRTL
  - custom transforms are run automatically

Also, add a bore method to BoringUtils that allows you to do one source to
multi-sink mapping in a single call. This adds a test that this is doing
the same thing as the equivalent call via disjoint addSink/addSource.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 16 insertions, 2 deletions

diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index fc71f2b0..e4bdda0b 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -5,6 +5,7 @@ package chisel3.testers
 import chisel3._
 import java.io._
 
+import chisel3.experimental.RunFirrtlTransform
 import firrtl.{Driver => _, _}
 
 object TesterDriver extends BackendCompilationUtilities {
@@ -25,6 +26,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // For now, dump the IR out to a file
     Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
+    val firrtlCircuit = Driver.toFirrtl(circuit)
 
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
@@ -37,9 +39,21 @@ object TesterDriver extends BackendCompilationUtilities {
     })
 
     // Compile firrtl
-    if (!compileFirrtlToVerilog(target, path)) {
-      return false
+    val transforms = circuit.annotations.collect { case anno: RunFirrtlTransform => anno.transformClass }.distinct
+      .filterNot(_ == classOf[Transform])
+      .map { transformClass: Class[_ <: Transform] => transformClass.newInstance() }
+    val annotations = circuit.annotations.map(_.toFirrtl).toList
+    val optionsManager = new ExecutionOptionsManager("chisel3") with HasChiselExecutionOptions with HasFirrtlOptions {
+      commonOptions = CommonOptions(topName = target, targetDirName = path.getAbsolutePath)
+      firrtlOptions = FirrtlExecutionOptions(compilerName = "verilog", annotations = annotations,
+                                             customTransforms = transforms,
+                                             firrtlCircuit = Some(firrtlCircuit))
     }
+    firrtl.Driver.execute(optionsManager) match {
+      case _: FirrtlExecutionFailure => return false
+      case _ =>
+    }
+
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
     if ((verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
         cppToExe(target, path)).! == 0) {