Move backend compilation utilities (#400)

* Move copyResourceToFile() to BackendCompilationUtilities.
* Move BackendCompilationUtilities into a firrtl util package.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
* Use new createTestDirectory. Fixes #452.

1 files changed, 4 insertions, 13 deletions

diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index bcbb9cd3..fd3ad9ba 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -5,18 +5,9 @@ package chisel3.testers
 import chisel3._
 import java.io._
 
+import firrtl.{Driver => _, _}
+
 object TesterDriver extends BackendCompilationUtilities {
-  /** Copy the contents of a resource to a destination file.
-    */
-  def copyResourceToFile(name: String, file: File) {
-    val in = getClass.getResourceAsStream(name)
-    if (in == null) {
-      throw new FileNotFoundException(s"Resource '$name'")
-    }
-    val out = new FileOutputStream(file)
-    Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write)
-    out.close()
-  }
 
   /** For use with modules that should successfully be elaborated by the
     * frontend, and which can be turned into executables with assertions. */
@@ -29,7 +20,7 @@ object TesterDriver extends BackendCompilationUtilities {
     // plus the quirks of Verilator's naming conventions
     val target = circuit.name
 
-    val path = createTempDirectory(target)
+    val path = createTestDirectory(target)
     val fname = new File(path, target)
 
     // For now, dump the IR out to a file
@@ -50,7 +41,7 @@ object TesterDriver extends BackendCompilationUtilities {
       return false
     }
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
+    if ((verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
         cppToExe(target, path)).! == 0) {
       executeExpectingSuccess(target, path)
     } else {