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| author | Jim Lawson | 2016-07-25 13:37:53 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-25 13:37:53 -0700 |
| commit | 3624751e2e63ba9f107c795529edfe48cf8340b2 (patch) | |
| tree | 951deec27b8a75d9d9c0eec0aee6fa08f80f9ae0 /src/main/scala/chisel3/package.scala | |
| parent | 50518f43cbd9c783633714a26ecdb0f2f18a1142 (diff) | |
| parent | 54cd58cbb435170dd2ed67dafe1cb1d769a799e8 (diff) | |
Merge branch 'master' into sdtwigg_connectwrap_renamechisel3
Diffstat (limited to 'src/main/scala/chisel3/package.scala')
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index d47ed890..9a79b109 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -100,7 +100,7 @@ package object chisel3 { implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { def B: Bool = Bool(x) } - + implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg |