diff options
| author | mergify[bot] | 2022-08-02 00:31:11 +0000 |
|---|---|---|
| committer | GitHub | 2022-08-02 00:31:11 +0000 |
| commit | 6b658d740d976c7706c53c756acd069262d9ef59 (patch) | |
| tree | c2d93170b29f51182c8139b017763bf8b971e998 /src/main/scala/chisel3/compatibility.scala | |
| parent | 5d70874eba009d9f17886a2edd19ce0fa02a77b3 (diff) | |
Remove remaining chiselNames (#2635) (#2656)
(cherry picked from commit 8538269a14e0d5a1163298a79aa43b77a380aabc)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/chisel3/compatibility.scala')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index f3754e00..d140725f 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,6 @@ * while moving to the more standard package naming convention `chisel3` (lowercase c). */ import chisel3._ // required for implicit conversions. -import chisel3.experimental.chiselName import chisel3.util.random.FibonacciLFSR import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage} @@ -617,7 +616,6 @@ package object Chisel { /** Generates a 16-bit linear feedback shift register, returning the register contents. * @param increment optional control to gate when the LFSR updates. */ - @chiselName def apply(increment: Bool = true.B): UInt = VecInit( FibonacciLFSR |