diff options
| author | Jim Lawson | 2017-02-07 15:40:26 -0800 |
|---|---|---|
| committer | GitHub | 2017-02-07 15:40:26 -0800 |
| commit | 6aa4c649c850a01f642c50ff222bd633aca7fe4b (patch) | |
| tree | 27686cb9947d50c8e51a84451fd8c36ac745ffe1 /src/main/scala/chisel3/compatibility.scala | |
| parent | 8974f749eea1a452ba732dd833376ef4283173a8 (diff) | |
Rename SeqMem to SyncReadMem. (#490)
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
Diffstat (limited to 'src/main/scala/chisel3/compatibility.scala')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index d338d9ab..e7b44dd7 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -157,8 +157,8 @@ package object Chisel { // scalastyle:ignore package.object.name val Mem = chisel3.core.Mem type MemBase[T <: Data] = chisel3.core.MemBase[T] type Mem[T <: Data] = chisel3.core.Mem[T] - val SeqMem = chisel3.core.SeqMem - type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + val SeqMem = chisel3.core.SyncReadMem + type SeqMem[T <: Data] = chisel3.core.SyncReadMem[T] val Module = chisel3.core.Module type Module = chisel3.core.Module |