Deprecate fromBits and clock/reset constructors (#583)

1 files changed, 29 insertions, 6 deletions

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 778d2c13..d64b3bb5 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -37,6 +37,26 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val Clock = chisel3.core.Clock
   type Clock = chisel3.core.Clock
 
+  // Implicit conversion to allow fromBits because it's being deprecated in chisel3
+  implicit class fromBitsable[T <: Data](val data: T) {
+    import chisel3.core.CompileOptions
+    import chisel3.internal.sourceinfo.SourceInfo
+
+    /** Creates an new instance of this type, unpacking the input Bits into
+      * structured data.
+      *
+      * This performs the inverse operation of toBits.
+      *
+      * @note does NOT assign to the object this is called on, instead creates
+      * and returns a NEW object (useful in a clone-and-assign scenario)
+      * @note does NOT check bit widths, may drop bits during assignment
+      * @note what fromBits assigs to must have known widths
+      */
+    def fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+      that.asTypeOf(data)
+    }
+  }
+
   type Aggregate = chisel3.core.Aggregate
   val Vec = chisel3.core.Vec
   type Vec[T <: Data] = chisel3.core.Vec[T]
@@ -155,7 +175,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   import chisel3.core.Param
   abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.core.BlackBox(params) {
     // This class auto-wraps the BlackBox with IO(...), allowing legacy code (where IO(...) wasn't
-    // required) to build. 
+    // required) to build.
     override def _autoWrapPorts() = {
       if (!_ioPortBound()) {
         IO(io)
@@ -176,10 +196,13 @@ package object Chisel {     // scalastyle:ignore package.object.name
     // This class auto-wraps the Module IO with IO(...), allowing legacy code (where IO(...) wasn't
     // required) to build.
     // Also provides the clock / reset constructors, which were used before withClock happened.
-    
-    def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions)
-    def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions)
-    def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions)
+
+    def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) =
+      this(Option(_clock), None)(moduleCompileOptions)
+    def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  =
+      this(None, Option(_reset))(moduleCompileOptions)
+    def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
+      this(Option(_clock), Option(_reset))(moduleCompileOptions)
 
     override def _autoWrapPorts() = {
       if (!_ioPortBound()) {
@@ -203,7 +226,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     // parameterized scope.
     def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
       chisel3.core.Reg(t)
-    
+
     /** Creates a register with optional next and initialization values.
       *
       * @param t: data type for the register