diff options
| author | Jack Koenig | 2021-04-29 16:18:06 -0700 |
|---|---|---|
| committer | GitHub | 2021-04-29 16:18:06 -0700 |
| commit | c5861176887bfa529277e686df09a42aeceb6cd7 (patch) | |
| tree | 82dc235e29ee615d063325eb66b96f54d652c4f6 /src/main/scala/chisel3/aop | |
| parent | 4d8fed00225d15221cf32177ea9147b20d0b91f7 (diff) | |
Scala 2.13 support (#1751)
Diffstat (limited to 'src/main/scala/chisel3/aop')
| -rw-r--r-- | src/main/scala/chisel3/aop/Select.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/chisel3/aop/injecting/InjectingAspect.scala | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala index e2689f39..b9ad808b 100644 --- a/src/main/scala/chisel3/aop/Select.scala +++ b/src/main/scala/chisel3/aop/Select.scala @@ -248,7 +248,7 @@ object Select { case other => } }) - predicatedConnects + predicatedConnects.toSeq } /** Selects all stop statements, and includes the predicates surrounding the stop statement @@ -264,7 +264,7 @@ object Select { case other => } }) - stops + stops.toSeq } /** Selects all printf statements, and includes the predicates surrounding the printf statement @@ -280,7 +280,7 @@ object Select { case other => } }) - printfs + printfs.toSeq } // Checks that a module has finished its construction @@ -321,7 +321,7 @@ object Select { } } catch { case e: ChiselException => i.getOptionRef.get match { - case l: LitArg => l.num.intValue().toString + case l: LitArg => l.num.intValue.toString } } diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala index 768680ed..c540fc83 100644 --- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala +++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala @@ -89,7 +89,7 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule]( Seq(other) } - InjectStatement(ModuleTarget(circuit, module.name), ir.Block(stmts), modules, annotations) + InjectStatement(ModuleTarget(circuit, module.name), ir.Block(stmts.toSeq), modules, annotations) }.toSeq } } |
