diff options
| author | Jim Lawson | 2016-09-30 12:13:58 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-30 12:13:58 -0700 |
| commit | db25e8180a53fb8f4912fd37b7a613e15a01564f (patch) | |
| tree | 8bb5597746002ac98641f394cee4c94e1d154aff /src/main/scala/chisel3/Driver.scala | |
| parent | 785620b1403d827986bf60c2a001d8d6f71eed72 (diff) | |
| parent | 6edbdf279257d656b5eac38d9de8645a068611bf (diff) | |
Merge pull request #265 from ucb-bar/gsdt
Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 5aeeef99..5e0a3a0f 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -47,7 +47,7 @@ trait BackendCompilationUtilities { * C++ sources and headers as well as a makefile to compile them. * * @param dutFile name of the DUT .v without the .v extension - * @param name of the top-level module in the design + * @param topModule of the top-level module in the design * @param dir output directory * @param vSources list of additional Verilog sources to compile * @param cppHarness C++ testharness to compile/link against |