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authorSchuyler Eldridge2019-08-27 22:11:45 -0400
committerGitHub2019-08-27 22:11:45 -0400
commit5bccb888fd3bd129b00e09f946bf820c17f7cc7f (patch)
treea1d7ac067875bd4d8062d6d748a8e04e2982d151 /src/main/scala/chisel3/Driver.scala
parenteccacc3d7a07208ff31e592b13c0dece1012dca2 (diff)
parentc485a3a89b80d7a5069f00a7cd8ebdfce0a84991 (diff)
Merge pull request #1160 from freechipsproject/issue-1159
Fix Stack Trace Trimming in Driver
Diffstat (limited to 'src/main/scala/chisel3/Driver.scala')
-rw-r--r--src/main/scala/chisel3/Driver.scala16
1 files changed, 5 insertions, 11 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a78cc92f..158ba65a 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -6,7 +6,7 @@ import chisel3.internal.ErrorLog
import chisel3.experimental.RawModule
import internal.firrtl._
import firrtl._
-import firrtl.options.{Phase, PhaseManager}
+import firrtl.options.{Phase, PhaseManager, StageError}
import firrtl.options.phases.DeletedWrapper
import firrtl.options.Viewer.view
import firrtl.annotations.JsonProtocol
@@ -226,16 +226,10 @@ object Driver extends BackendCompilationUtilities {
val annosx = try {
phases.foldLeft(annos)( (a, p) => p.transform(a) )
} catch {
- case ce: ChiselException =>
- val stackTrace = if (!optionsManager.chiselOptions.printFullStackTrace) {
- ce.chiselStackTrace
- } else {
- val sw = new StringWriter
- ce.printStackTrace(new PrintWriter(sw))
- sw.toString
- }
- Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex line.size.limit
- annos
+ /* ChiselStage and FirrtlStage can throw StageError. Since Driver is not a StageMain, it cannot catch these. While
+ * Driver is deprecated and removed in 3.2.1+, the Driver catches all errors.
+ */
+ case e: StageError => annos
}
view[ChiselExecutionResult](annosx)