summaryrefslogtreecommitdiff
path: root/src/main/scala/Chisel
diff options
context:
space:
mode:
authorAndrew Waterman2015-08-03 15:11:22 -0700
committerAndrew Waterman2015-08-03 15:11:22 -0700
commitcb92cc4f8b46bdcbd159f0aeb9b0e556ee55f959 (patch)
treeea601bc61e820c301b193047448a5e1e848cef87 /src/main/scala/Chisel
parent9faa11889c3200ac3751263fd3ddb04f56e2408f (diff)
Don't zero-initialize for Wire(init=...)
Diffstat (limited to 'src/main/scala/Chisel')
-rw-r--r--src/main/scala/Chisel/Core.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 9f7eb2c2..3f6c197d 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -341,7 +341,8 @@ object Wire {
pushCommand(DefWire(x, x.toType))
if (init != null)
pushCommand(Connect(x.lref, init.ref))
- x.flatten.foreach(e => e := e.makeLit(0,1))
+ else
+ x.flatten.foreach(e => e := e.makeLit(0,1))
x
}
}