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authorAndrew Waterman2016-01-27 15:20:00 -0800
committerAndrew Waterman2016-01-27 15:20:00 -0800
commit22d302ad066d8a073e44289ba4876a165ea56b05 (patch)
treea3fe2f7ec86f6a06e28b44d000abae0a0ded1fca /src/main/scala/Chisel
parent71f45a6df99cb86ada1ad9d091a38e01b698a863 (diff)
Remove unsupported FIRRTL node bit(); use bits()
Diffstat (limited to 'src/main/scala/Chisel')
-rw-r--r--src/main/scala/Chisel/Bits.scala2
-rw-r--r--src/main/scala/Chisel/internal/firrtl/IR.scala1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 3974d05d..6062f2de 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -39,7 +39,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
if (isLit()) {
Bool(((litValue() >> x.toInt) & 1) == 1)
} else {
- pushOp(DefPrim(Bool(), BitSelectOp, this.ref, ILit(x)))
+ pushOp(DefPrim(Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
}
}
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index ec9b9e36..1bc3ad89 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -25,7 +25,6 @@ object PrimOp {
val BitXorOp = PrimOp("xor")
val BitNotOp = PrimOp("not")
val ConcatOp = PrimOp("cat")
- val BitSelectOp = PrimOp("bit")
val BitsExtractOp = PrimOp("bits")
val LessOp = PrimOp("lt")
val LessEqOp = PrimOp("leq")