diff options
| author | Andrew Waterman | 2016-01-28 12:15:53 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-28 12:15:53 -0800 |
| commit | 7eff2b0a16e1ca982c227bd498720981c883686b (patch) | |
| tree | 767a04718b16750b33dd4e2d629d3e836bb7f637 /src/main/scala/Chisel/util | |
| parent | 6d37cc8b9d731fa4c844f097b11057c46771961b (diff) | |
| parent | 41674d5e130f64d7489fdb8583b8f4ad88b64aeb (diff) | |
Merge branch 'master' into scalastyle
Diffstat (limited to 'src/main/scala/Chisel/util')
| -rw-r--r-- | src/main/scala/Chisel/util/Arbiter.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/Chisel/util/Decoupled.scala | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala index 119b9f5a..2747640f 100644 --- a/src/main/scala/Chisel/util/Arbiter.scala +++ b/src/main/scala/Chisel/util/Arbiter.scala @@ -7,7 +7,7 @@ package Chisel /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { - val in = Vec(Decoupled(gen), n).flip + val in = Vec(n, Decoupled(gen)).flip val out = Decoupled(gen) val chosen = UInt(OUTPUT, log2Up(n)) } diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala index b1505887..ca000af9 100644 --- a/src/main/scala/Chisel/util/Decoupled.scala +++ b/src/main/scala/Chisel/util/Decoupled.scala @@ -82,7 +82,7 @@ class Queue[T <: Data](gen: T, val entries: Int, { val io = new QueueIO(gen, entries) - val ram = Mem(gen, entries) + val ram = Mem(entries, gen) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = Reg(init=Bool(false)) |