Implement first draft of new FIRRTL changes

3 files changed, 27 insertions, 17 deletions

diff --git a/src/main/scala/Chisel/internal/Builder.scala b/src/main/scala/Chisel/internal/Builder.scala
index 991a442f..7e72b5e1 100644
--- a/src/main/scala/Chisel/internal/Builder.scala
+++ b/src/main/scala/Chisel/internal/Builder.scala
@@ -50,7 +50,8 @@ private[Chisel] trait HasId {
   private[Chisel] def setRef(imm: Arg) = _refMap.setRef(this, imm)
   private[Chisel] def setRef(name: String) = _refMap.setRef(this, name)
   private[Chisel] def setRef(parent: HasId, name: String) = _refMap.setField(parent, this, name)
-  private[Chisel] def setRef(parent: HasId, index: Int) = _refMap.setIndex(parent, this, index)
+  private[Chisel] def setRef(parent: HasId, index: Int) = _refMap.setIndex(parent, this, ILit(index))
+  private[Chisel] def setRef(parent: HasId, index: UInt) = _refMap.setIndex(parent, this, index.ref)
   private[Chisel] def getRef = _refMap(this)
 }
 
@@ -66,7 +67,7 @@ class RefMap {
   private[Chisel] def setField(parentid: HasId, id: HasId, name: String): Unit =
     _refmap(id._id) = Slot(Node(parentid), name)
 
-  private[Chisel] def setIndex(parentid: HasId, id: HasId, index: Int): Unit =
+  private[Chisel] def setIndex(parentid: HasId, id: HasId, index: Arg): Unit =
     _refmap(id._id) = Index(Node(parentid), index)
 
   def apply(id: HasId): Arg = _refmap(id._id)
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index c46f14ca..8597454a 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
@@ -12,15 +12,14 @@ private class Emitter(circuit: Circuit) {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
     case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
-    case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
-    case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
-    case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
-    case e: DefAccessor[_] => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
-    case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
-    case e: BulkConnect => s"${e.loc1.fullName(ctx)} <> ${e.loc2.fullName(ctx)}"
-    case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
-    case e: Stop => s"stop(${e.clk.fullName(ctx)}, ${e.ret})"
-    case e: Printf => s"""printf(${e.clk.fullName(ctx)}, "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
+    case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}"
+    case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]"
+    case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]"
+    case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
+    case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
+    case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
+    case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
+    case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
     case e: DefInstance => {
       val modName = moduleMap.getOrElse(e.id.name, e.id.name)
       s"inst ${e.name} of $modName"
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index be61d67b..5612f1af 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -90,9 +90,9 @@ case class Slot(imm: Node, name: String) extends Arg {
   override def fullName(ctx: Component): String =
     if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}"
 }
-case class Index(imm: Arg, value: Int) extends Arg {
+case class Index(imm: Arg, value: Arg) extends Arg {
   def name: String = s"[$value]"
-  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[$value]"
+  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
 }
 
 object Width {
@@ -132,6 +132,16 @@ sealed case class KnownWidth(value: Int) extends Width {
   override def toString: String = value.toString
 }
 
+sealed abstract class MemPortDirection(name: String) {
+  override def toString: String = name
+}
+object MemPortDirection {
+  object READ extends MemPortDirection("read")
+  object WRITE extends MemPortDirection("write")
+  object RDWR extends MemPortDirection("rdwr")
+  object INFER extends MemPortDirection("infer")
+}
+
 abstract class Command
 abstract class Definition extends Command {
   def id: HasId
@@ -139,10 +149,10 @@ abstract class Definition extends Command {
 }
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
-case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
-case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
-case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
-case class DefAccessor[T <: Data](id: T, source: Node, direction: Direction, index: Arg) extends Definition
+case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefMemory(id: HasId, t: Data, size: Int) extends Definition
+case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition
+case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
 case class DefPoison[T <: Data](id: T) extends Definition
 case class WhenBegin(pred: Arg) extends Command