diff options
| author | Andrew Waterman | 2016-01-27 15:18:49 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-27 15:18:49 -0800 |
| commit | 2a3b5fc59c732d85aafda78f2fb21368dc4a5660 (patch) | |
| tree | ed56cd131bc2b80140b71b4467c1e05d235653a0 /src/main/scala/Chisel/internal/firrtl/IR.scala | |
| parent | 9017ec37d0eb7bb3bd10ed7863c0706ff1020cd9 (diff) | |
New FIRRTL syntax for reg
Diffstat (limited to 'src/main/scala/Chisel/internal/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 5612f1af..ec9b9e36 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -149,7 +149,8 @@ abstract class Definition extends Command { } case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition case class DefWire(id: Data) extends Definition -case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefReg(id: Data, clock: Arg) extends Definition +case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int) extends Definition case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition |