From 2a3b5fc59c732d85aafda78f2fb21368dc4a5660 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:18:49 -0800
Subject: New FIRRTL syntax for reg

---
 src/main/scala/Chisel/internal/firrtl/IR.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/internal/firrtl/IR.scala')

diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 5612f1af..ec9b9e36 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -149,7 +149,8 @@ abstract class Definition extends Command {
 }
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
-case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefReg(id: Data, clock: Arg) extends Definition
+case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
 case class DefMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
-- 
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