Add support for printf and asserts, add testbench for asserts and printf

2 files changed, 4 insertions, 0 deletions

diff --git a/src/main/scala/Chisel/firrtl/Emitter.scala b/src/main/scala/Chisel/firrtl/Emitter.scala
index bcc566c5..1d0f4ddc 100644
--- a/src/main/scala/Chisel/firrtl/Emitter.scala
+++ b/src/main/scala/Chisel/firrtl/Emitter.scala
@@ -19,6 +19,8 @@ private class Emitter(circuit: Circuit) {
     case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
     case e: BulkConnect => s"${e.loc1.fullName(ctx)} <> ${e.loc2.fullName(ctx)}"
     case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
+    case e: Stop => s"stop(${e.clk.fullName(ctx)}, ${e.ret})"
+    case e: Printf => s"""printf(${e.clk.fullName(ctx)}, "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
     case e: DefInstance => {
       val modName = moduleMap.getOrElse(e.id.name, e.id.name)
       s"inst ${e.name} of $modName"
diff --git a/src/main/scala/Chisel/firrtl/IR.scala b/src/main/scala/Chisel/firrtl/IR.scala
index 458e6ac5..8cc31b54 100644
--- a/src/main/scala/Chisel/firrtl/IR.scala
+++ b/src/main/scala/Chisel/firrtl/IR.scala
@@ -151,6 +151,8 @@ case class WhenEnd() extends Command
 case class Connect(loc: Node, exp: Arg) extends Command
 case class BulkConnect(loc1: Node, loc2: Node) extends Command
 case class ConnectInit(loc: Node, exp: Arg) extends Command
+case class Stop(clk: Arg, ret: Int) extends Command
+case class Printf(clk: Arg, format: String, ids: Seq[Arg]) extends Command
 case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
 case class Port(id: Data, dir: Direction)