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authorAndrew Waterman2016-01-28 12:25:17 -0800
committerAndrew Waterman2016-01-28 12:25:17 -0800
commita6cdcecb7920b661de09948609674b89f21b985f (patch)
tree11fb062f11c784287a0c63f933a0e3d9f863b702 /src/main/scala/Chisel/Module.scala
parentccc88bbd9d462f04fe1dd39327349aeea8de9d3c (diff)
parentf9977fb4e5508032c3e17d201f747e71a32b9311 (diff)
Merge branch 'master' into modrefactor
Diffstat (limited to 'src/main/scala/Chisel/Module.scala')
-rw-r--r--src/main/scala/Chisel/Module.scala8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 2a0f29db..463c2f81 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -20,16 +20,12 @@ object Module {
def apply[T <: Module](bc: => T): T = {
val parent = dynamicContext.currentModule
val m = bc.setRefs()
- // init module outputs
- m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
- yield Connect(p.lref, p.fromInt(0).ref))
+ m._commands.prepend(DefInvalid(m.io.ref)) // init module outputs
dynamicContext.currentModule = parent
val ports = m.computePorts
Builder.components += Component(m, m.name, ports, m._commands)
pushCommand(DefInstance(m, ports))
- // init instance inputs
- for (p <- m.io.flatten; if p.dir == INPUT)
- p := p.fromInt(0)
+ pushCommand(DefInvalid(m.io.ref)) // init instance inputs
m.connectImplicitIOs()
}
}