Merge pull request #57 from ucb-bar/stylechisel

Fix new style errors

1 files changed, 3 insertions, 3 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index 64356b21..dd78ab8d 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -55,7 +55,7 @@ trait BackendCompilationUtilities {
         "--Wno-fatal",
         "--trace",
         "-O2",
-        "+define+TOP_TYPE=V"+prefix,
+        "+define+TOP_TYPE=V" + prefix,
         "-CFLAGS", s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$prefix -include ${vH.toString}""",
         "-Mdir", dir.toString,
         "--exe", cppHarness.toString)
@@ -81,14 +81,14 @@ trait BackendCompilationUtilities {
 
 object Driver extends FileSystemUtilities with BackendCompilationUtilities {
 
-  /** Elaborates the Module specified in the gen function into a Circuit 
+  /** Elaborates the Module specified in the gen function into a Circuit
     *
     *  @param gen a function that creates a Module hierarchy
     *
     *  @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
     */
   def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
-  
+
   def emit[T <: Module](gen: () => T): String = elaborate(gen).emit
 
   def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {