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authorAndrew Waterman2015-08-05 17:28:14 -0700
committerAndrew Waterman2015-08-05 17:28:14 -0700
commit25c94f85be5b62797f693d63f65e3a2269ddefb2 (patch)
tree54743ce9137e24c60a84ad81ea187879172300dd /src/main/scala/Chisel/Driver.scala
parentbfc80f6e220ea75c717a7fb5ab4ffad84380a7f8 (diff)
Name output files according to ChiselConfig.toString
Diffstat (limited to 'src/main/scala/Chisel/Driver.scala')
-rw-r--r--src/main/scala/Chisel/Driver.scala17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index 5edda019..20463344 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -87,7 +87,7 @@ object Driver extends FileSystemUtilities {
val world = if(collectConstraints) config.toCollector else config.toInstance
val p = Parameters.root(world)
config.topConstraints.foreach(c => p.constrain(c))
- elaborate(gen, p)
+ elaborate(gen, p, config)
}
/** Elaborates the circuit specified in the gen function, optionally uses
@@ -95,14 +95,17 @@ object Driver extends FileSystemUtilities {
* TODO: Distinguish between cases where we dump to file vs return IR for
* use by other Drivers.
*/
- def elaborate[T <: Module](gen: () => T, p: Parameters = Parameters.empty) {
+ private[Chisel] def elaborateWrappedModule[T <: Module](gen: () => T, p: Parameters, c: Option[ChiselConfig]) {
try {
ChiselError.clear()
ChiselError.info("Elaborating design...")
- val ir = build(Module(gen())(p))
+ val ir = build(gen())
ChiselError.info("Done elaborating.")
- val name = ir.main +"."+ p.getClass.getSimpleName
+ val name = c match {
+ case None => ir.main
+ case Some(config) => s"${ir.main}.$config"
+ }
createOutputFile(s"$name.knb", p.getKnobs)
createOutputFile(s"$name.cst", p.getConstraints)
createOutputFile(s"$name.prm", Dump.getDump)
@@ -111,4 +114,10 @@ object Driver extends FileSystemUtilities {
ChiselError.report
}
}
+ def elaborate[T <: Module](gen: () => T): Unit =
+ elaborate(gen, Parameters.empty)
+ def elaborate[T <: Module](gen: () => T, p: Parameters): Unit =
+ elaborateWrappedModule(() => Module(gen())(p), p, None)
+ def elaborate[T <: Module](gen: () => T, p: Parameters, c: ChiselConfig): Unit =
+ elaborateWrappedModule(() => Module(gen())(p), p, Some(c))
}