diff options
| author | Andrew Waterman | 2016-01-23 16:03:29 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-23 16:03:29 -0800 |
| commit | 780e7c4d2a7e88a3a8ce6f5d7e75e62af6580c6d (patch) | |
| tree | 94abfbd655d4760c551869919ae23f97c245da9d /src/main/scala/Chisel/CoreUtil.scala | |
| parent | 57c1770a964c44b4211453ab6f7f41289f21cd50 (diff) | |
| parent | 544afdebc4d1b441e57123bd67bc48e8c036ffbb (diff) | |
Merge pull request #92 from ucb-bar/moveFIRRTL
Move firrtl subpackage to inside internal subpackage.
Diffstat (limited to 'src/main/scala/Chisel/CoreUtil.scala')
| -rw-r--r-- | src/main/scala/Chisel/CoreUtil.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala index 9027711b..eed90410 100644 --- a/src/main/scala/Chisel/CoreUtil.scala +++ b/src/main/scala/Chisel/CoreUtil.scala @@ -4,7 +4,7 @@ package Chisel import internal._ import internal.Builder.pushCommand -import firrtl._ +import internal.firrtl._ object assert { /** Checks for a condition to be valid in the circuit at all times. If the |