diff options
| author | Andrew Waterman | 2015-07-29 00:38:53 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-07-29 00:38:53 -0700 |
| commit | 917ef93d6add8dabebccb31e7768a887609f6502 (patch) | |
| tree | 1cfcbf88366bafe0ece4c32a4bf138e9012d2a37 /src/main/scala/Chisel/Core.scala | |
| parent | 75f54a3f873f168a7811da88ba1d3d59c9844659 (diff) | |
Fix Bundle port ordering
Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 64c0e0f6..37f1f35a 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -936,7 +936,7 @@ object Bundle { class Bundle(dirArg: Direction = NO_DIR) extends Aggregate(dirArg) { def toPorts: Seq[Port] = - elements.map(_._2.toPort).toSeq + elements.map(_._2.toPort).toSeq.reverse def toType: BundleType = BundleType(this.toPorts, isFlipVar) |