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authorPalmer Dabbelt2015-10-21 16:00:19 -0700
committerPalmer Dabbelt2015-10-21 16:00:19 -0700
commit90bde8730fd71c3a5fc0b026064a4f1004e43d0f (patch)
tree99b1e01d507e4d71f45e88d65d452bd65566a0bd /src/main/scala/Chisel/Core.scala
parentd40c0009383dc8c8d9c8514478a5b406a5e789a8 (diff)
parentcff13b54421095190314c724896842abf4dd2dc1 (diff)
Merge pull request #27 from ucb-bar/scalastyle-types
Add explicit types for public methods
Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
-rw-r--r--src/main/scala/Chisel/Core.scala24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 486f0ff3..6fb0fb25 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -9,18 +9,18 @@ import Builder.dynamicContext
import PrimOp._
sealed abstract class Direction(name: String) {
- override def toString = name
+ override def toString: String = name
def flip: Direction
}
-object INPUT extends Direction("input") { def flip = OUTPUT }
-object OUTPUT extends Direction("output") { def flip = INPUT }
-object NO_DIR extends Direction("?") { def flip = NO_DIR }
+object INPUT extends Direction("input") { override def flip: Direction = OUTPUT }
+object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
+object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
// REVIEW TODO: Should this actually be part of the RTL API? RTL should be
// considered untouchable from a debugging standpoint?
object debug {
// TODO:
- def apply (arg: Data) = arg
+ def apply (arg: Data): Data = arg
}
/** This forms the root of the type system for wire data types. The data value
@@ -70,7 +70,7 @@ abstract class Data(dirArg: Direction) extends HasId {
def isLit(): Boolean = litArg.isDefined
def width: Width
- final def getWidth = width.get
+ final def getWidth: Int = width.get
// REVIEW TODO: should this actually be part of the Data interface? this is
// an Aggregate function?
@@ -721,7 +721,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
def ## (other: Bits): UInt = Cat(this, other)
// REVIEW TODO: This just _looks_ wrong.
- override def toBits = asUInt
+ override def toBits: UInt = asUInt
override def fromBits(n: Bits): this.type = {
val res = Wire(this).asInstanceOf[this.type]
@@ -814,8 +814,8 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
}
// TODO: refactor to share documentation with Num or add independent scaladoc
- def unary_- = UInt(0) - this
- def unary_-% = UInt(0) -% this
+ def unary_- : UInt = UInt(0) - this
+ def unary_-% : UInt = UInt(0) -% this
def +& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), AddOp, other)
def + (other: UInt): UInt = this +% other
def +% (other: UInt): UInt = binop(UInt(this.width max other.width), AddModOp, other)
@@ -832,9 +832,9 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
def ^ (other: UInt): UInt = binop(UInt(this.width max other.width), BitXorOp, other)
// REVIEW TODO: Can this be defined on Bits?
- def orR = this != UInt(0)
- def andR = ~this === UInt(0)
- def xorR = redop(XorReduceOp)
+ def orR: Bool = this != UInt(0)
+ def andR: Bool = ~this === UInt(0)
+ def xorR: Bool = redop(XorReduceOp)
def < (other: UInt): Bool = compop(LessOp, other)
def > (other: UInt): Bool = compop(GreaterOp, other)