diff options
| author | Andrew Waterman | 2015-08-13 12:38:12 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-08-13 15:00:33 -0700 |
| commit | 2b85e2d1b2f45f6977f626f1af5b2ef9a7987fde (patch) | |
| tree | 57977f6fb8decf6c2ad1b805216ba5894140b62b /src/main/scala/Chisel/Core.scala | |
| parent | a20354fd7b6f0e28a9b81cab09a0b9d2a4aa0244 (diff) | |
FP stuff doesn't belong in Data
Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index a8e270f6..537c0197 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -2,8 +2,6 @@ package Chisel import scala.collection.immutable.ListMap import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap} import java.lang.reflect.Modifier._ -import java.lang.Double.longBitsToDouble -import java.lang.Float.intBitsToFloat import Builder.pushCommand import Builder.pushOp import Builder.dynamicContext @@ -79,8 +77,6 @@ abstract class Data(dirArg: Direction) extends HasId { def litArg(): Option[LitArg] = None def litValue(): BigInt = litArg.get.num def isLit(): Boolean = litArg.isDefined - def floLitValue: Float = intBitsToFloat(litValue().toInt) - def dblLitValue: Double = longBitsToDouble(litValue().toLong) def width: Width final def getWidth = width.get |