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authorAndrew Waterman2016-01-17 17:20:49 -0800
committerAndrew Waterman2016-01-23 21:14:19 -0800
commit34a1abcd81bd3b2d7d264468345572009edfad27 (patch)
tree0dbaa05d8142d370d4df35d6999416325e1c0c99 /src/main/scala/Chisel/Aggregate.scala
parent86a6c6bcdc349f40dcc31bce1931dc7c427da674 (diff)
Implement first draft of new FIRRTL changes
Diffstat (limited to 'src/main/scala/Chisel/Aggregate.scala')
-rw-r--r--src/main/scala/Chisel/Aggregate.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 63df8135..f510a913 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -141,7 +141,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
*/
def apply(idx: UInt): T = {
val x = gen
- pushCommand(DefAccessor(x, Node(this), NO_DIR, idx.ref))
+ x.setRef(this, idx)
x
}