Add scanLeftOr and scanRightOr utilies (#2407) (#2437)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 73d3c26029c07c17ce179dfead092eab4fb8ae2c)

Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
new file mode 100644
index 00000000..6c8eb4b4
--- /dev/null
+++ b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: Apache-2.0
+
+import chisel3._
+import chisel3.util._
+import chiseltest._
+import chiseltest.formal._
+import org.scalatest.flatspec.AnyFlatSpec
+import scala.math.min
+
+class ScanLeftOrTestModule(width: Int) extends Module {
+  val input = IO(Input(UInt(width.W)))
+
+  var lsb = false.B
+  val vec = for(b <- input.asBools) yield {
+    val cur = b || lsb
+    lsb = cur
+    cur
+  }
+  val ref = VecInit(vec).asUInt
+
+  val testee = scanLeftOr(input)
+
+  assert(testee === ref)
+}
+
+class ScanRightOrTestModule(width: Int) extends Module {
+  val input = IO(Input(UInt(width.W)))
+
+  val ref = Reverse(scanLeftOr(Reverse(input)))
+  val testee = scanRightOr(input)
+
+  assert(testee === ref)
+}
+
+class scanOrTest extends AnyFlatSpec with ChiselScalatestTester with Formal {
+  "scanLeftOr" should "compute correctly" in {
+    for(i <- 1 to 16) {
+      verify(new ScanLeftOrTestModule(i), Seq(BoundedCheck(1)))
+    }
+  }
+
+  "scanRightOr" should "compute correctly" in {
+    for(i <- 1 to 16) {
+      verify(new ScanRightOrTestModule(i), Seq(BoundedCheck(1)))
+    }
+  }
+}