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authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala')
-rw-r--r--integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
index 6c8eb4b4..d0f16701 100644
--- a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
+++ b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala
@@ -11,7 +11,7 @@ class ScanLeftOrTestModule(width: Int) extends Module {
val input = IO(Input(UInt(width.W)))
var lsb = false.B
- val vec = for(b <- input.asBools) yield {
+ val vec = for (b <- input.asBools) yield {
val cur = b || lsb
lsb = cur
cur
@@ -34,13 +34,13 @@ class ScanRightOrTestModule(width: Int) extends Module {
class scanOrTest extends AnyFlatSpec with ChiselScalatestTester with Formal {
"scanLeftOr" should "compute correctly" in {
- for(i <- 1 to 16) {
+ for (i <- 1 to 16) {
verify(new ScanLeftOrTestModule(i), Seq(BoundedCheck(1)))
}
}
"scanRightOr" should "compute correctly" in {
- for(i <- 1 to 16) {
+ for (i <- 1 to 16) {
verify(new ScanRightOrTestModule(i), Seq(BoundedCheck(1)))
}
}