Merge branch '3.5.x' into 3.5-release

1 files changed, 4 insertions, 4 deletions

diff --git a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala
index 35d1a299..20f3443a 100644
--- a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala
+++ b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala
@@ -10,12 +10,12 @@ import firrtl.annotations.MemoryArrayInitAnnotation
 import org.scalatest.flatspec.AnyFlatSpec
 
 class MemFormalSpec extends AnyFlatSpec with ChiselScalatestTester with Formal {
-  behavior of "SyncReadMem read enable"
+  behavior.of("SyncReadMem read enable")
 
   private def check(mod: Boolean => ReadEnTestModule, alwaysEnabeld: Boolean = false): Unit = {
     // we first check that the read is enabled when it should be
     verify(mod(true), Seq(BoundedCheck(4)))
-    if(!alwaysEnabeld) {
+    if (!alwaysEnabeld) {
       // now we check that it is disabled, when it should be
       // however, note that this check is not exhaustive/complete!
       assertThrows[FailedBoundedCheckException] {
@@ -65,9 +65,9 @@ abstract class ReadEnTestModule(testShouldRead: Boolean) extends Module {
   })
 
   // the first cycle after reset, the data will be arbitrary
-  val firstCycle = RegNext(false.B, init=true.B)
+  val firstCycle = RegNext(false.B, init = true.B)
 
-  if(testShouldRead) {
+  if (testShouldRead) {
     when(!firstCycle && RegNext(shouldRead)) {
       verification.assert(out === RegNext(addr))
     }