diff options
| author | mergify[bot] | 2022-10-25 01:58:03 +0000 |
|---|---|---|
| committer | GitHub | 2022-10-25 01:58:03 +0000 |
| commit | 2f890aabc1ecf04c6efcb84cee4f00da67be6a53 (patch) | |
| tree | f913d335a49fa5394ff4435018277fd00e458235 /integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala | |
| parent | f86c1ff7b39146f23cd1959bcc63dcb3b0b27125 (diff) | |
Add Scalafmt for mill (backport #2805) (#2807)
* Add Scalafmt for mill (#2805)
* add scalafmt for test in mill build system.
* reformat codes in integration-tests
(cherry picked from commit d881fd29d7af91a7c514565b4b21797f1e44fbdb)
# Conflicts:
# build.sc
# integration-tests/src/test/scala/chiselTests/util/experimental/BitPat.scala
* Resolve backport conflicts
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala')
| -rw-r--r-- | integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala index 35d1a299..20f3443a 100644 --- a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala +++ b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala @@ -10,12 +10,12 @@ import firrtl.annotations.MemoryArrayInitAnnotation import org.scalatest.flatspec.AnyFlatSpec class MemFormalSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { - behavior of "SyncReadMem read enable" + behavior.of("SyncReadMem read enable") private def check(mod: Boolean => ReadEnTestModule, alwaysEnabeld: Boolean = false): Unit = { // we first check that the read is enabled when it should be verify(mod(true), Seq(BoundedCheck(4))) - if(!alwaysEnabeld) { + if (!alwaysEnabeld) { // now we check that it is disabled, when it should be // however, note that this check is not exhaustive/complete! assertThrows[FailedBoundedCheckException] { @@ -65,9 +65,9 @@ abstract class ReadEnTestModule(testShouldRead: Boolean) extends Module { }) // the first cycle after reset, the data will be arbitrary - val firstCycle = RegNext(false.B, init=true.B) + val firstCycle = RegNext(false.B, init = true.B) - if(testShouldRead) { + if (testShouldRead) { when(!firstCycle && RegNext(shouldRead)) { verification.assert(out === RegNext(addr)) } |
