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| author | Jack | 2022-02-08 02:11:51 +0000 |
|---|---|---|
| committer | Jack | 2022-02-08 02:11:51 +0000 |
| commit | 4da4f252c3d7c834e13bb8e91a69cfe772996452 (patch) | |
| tree | 5acc86ebf6c429efc051954c6977ed2394498dbc /docs/src | |
| parent | 93d17165cc5339de3e2dc7cd9e10dd3634b49bac (diff) | |
| parent | 9d1e2082df4ecb2942a28b7039eb2ff36953380c (diff) | |
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'docs/src')
| -rw-r--r-- | docs/src/cookbooks/cookbook.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index d4cf3030..ec7e9ed2 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -440,7 +440,7 @@ chisel3.stage.ChiselStage.emitVerilog(new CountBits(4)) ### How do I get Chisel to name signals properly in blocks like when/withClockAndReset? -Use the compiler plugin, and check out the [Naming Cookbook](#naming) if that still does not do what you want. +Use the compiler plugin, and check out the [Naming Cookbook](naming) if that still does not do what you want. ### How do I get Chisel to name the results of vector reads properly? Currently, name information is lost when using dynamic indexing. For example: |