diff options
| author | Carlos Eduardo | 2021-04-14 22:38:41 -0300 |
|---|---|---|
| committer | GitHub | 2021-04-14 18:38:41 -0700 |
| commit | f39ec2ef5a3b2140b43d631056c2f974ca1895d5 (patch) | |
| tree | 7108627f257d65585ba39fcb8af936f611102913 /docs/src/explanations/sequential-circuits.md | |
| parent | 6e22d91ed31206292f9f8b02a89fe18885ad602d (diff) | |
Fix doc formatting and generation (#1863)
* Remove space between backticks and language
* Make code examples in memories explanation work
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'docs/src/explanations/sequential-circuits.md')
| -rw-r--r-- | docs/src/explanations/sequential-circuits.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/src/explanations/sequential-circuits.md b/docs/src/explanations/sequential-circuits.md index 938416ac..36bbb1aa 100644 --- a/docs/src/explanations/sequential-circuits.md +++ b/docs/src/explanations/sequential-circuits.md @@ -11,7 +11,7 @@ import chisel3._ val in = Bool() ``` The simplest form of state element supported by Chisel is a positive edge-triggered register, which can be instantiated as: -``` scala mdoc:compile-only +```scala mdoc:compile-only val reg = RegNext(in) ``` This circuit has an output that is a copy of the input signal `in` delayed by one clock cycle. Note that we do not have to specify the type of Reg as it will be automatically inferred from its input when instantiated in this way. In the current version of Chisel, clock and reset are global signals that are implicitly included where needed. |