Fix doc formatting and generation (#1863)

* Remove space between backticks and language
* Make code examples in memories explanation work

Co-authored-by: Jack Koenig <koenig@sifive.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/docs/src/explanations/polymorphism-and-parameterization.md b/docs/src/explanations/polymorphism-and-parameterization.md
index 94b896b1..9b69ed05 100644
--- a/docs/src/explanations/polymorphism-and-parameterization.md
+++ b/docs/src/explanations/polymorphism-and-parameterization.md
@@ -231,7 +231,10 @@ class X[T <: BaseModule with MyAdder](genT: => T) extends Module {
 println(ChiselStage.emitVerilog(new X(new Mod1)))
 println(ChiselStage.emitVerilog(new X(new Mod2)))
 ```
-```scala mdoc:passthrough
-println(ChiselStage.emitVerilog(new X(new Mod1)))
-println(ChiselStage.emitVerilog(new X(new Mod2)))
+
+Output:
+
+```scala mdoc:verilog
+ChiselStage.emitVerilog(new X(new Mod1))
+ChiselStage.emitVerilog(new X(new Mod2))
 ```