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authorCarlos Eduardo2021-04-14 22:38:41 -0300
committerGitHub2021-04-14 18:38:41 -0700
commitf39ec2ef5a3b2140b43d631056c2f974ca1895d5 (patch)
tree7108627f257d65585ba39fcb8af936f611102913 /docs/src/explanations/memories.md
parent6e22d91ed31206292f9f8b02a89fe18885ad602d (diff)
Fix doc formatting and generation (#1863)
* Remove space between backticks and language * Make code examples in memories explanation work Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'docs/src/explanations/memories.md')
-rw-r--r--docs/src/explanations/memories.md40
1 files changed, 20 insertions, 20 deletions
diff --git a/docs/src/explanations/memories.md b/docs/src/explanations/memories.md
index 09ac4c8d..1f2f83be 100644
--- a/docs/src/explanations/memories.md
+++ b/docs/src/explanations/memories.md
@@ -10,36 +10,36 @@ Chisel provides facilities for creating both read only and read/write memories.
## ROM
-Users can define read only memories with a `Vec`:
+Users can define read-only memories by constructing a `Vec` with `VecInit`.
+`VecInit` can except either a variable-argument number of `Data` literals or a `Seq[Data]` literals that initialize the ROM.
```scala mdoc:invisible
import chisel3._
+// This is bad, don't do this, use a val
+def counter = util.Counter(true.B, 4)._1
+val Pi = 3.14
+def sin(t: Double): Double = t // What should this be?
```
-``` scala mdoc:compile-only
- VecInit(inits: Seq[T])
- VecInit(elt0: T, elts: T*)
-```
-
-where `inits` is a sequence of initial `Data` literals that initialize the ROM. For example, users cancreate a small ROM initialized to 1, 2, 4, 8 and loop through all values using a counter as an address generator as follows:
+For example, users can create a small ROM initialized to 1, 2, 4, 8 and loop through all values using a counter as an address generator as follows:
-``` scala mdoc:compile-only
- val m = VecInit(Array(1.U, 2.U, 4.U, 8.U))
- val r = m(counter(m.length.U))
+```scala mdoc:compile-only
+val m = VecInit(1.U, 2.U, 4.U, 8.U)
+val r = m(counter(m.length.U))
```
We can create an *n* value sine lookup table using a ROM initialized as follows:
-``` scala mdoc:silent
- def sinTable(amp: Double, n: Int) = {
- val times =
- (0 until n).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
- val inits =
- times.map(t => round(amp * sin(t)).asSInt(32.W))
- VecInit(inits)
- }
- def sinWave(amp: Double, n: Int) =
- sinTable(amp, n)(counter(n.U))
+```scala mdoc:compile-only
+def sinTable(amp: Double, n: Int) = {
+ val times =
+ (0 until n).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
+ val inits =
+ times.map(t => Math.round(amp * sin(t)).asSInt(32.W))
+ VecInit(inits)
+}
+def sinWave(amp: Double, n: Int) =
+ sinTable(amp, n)(counter(n.U))
```
where `amp` is used to scale the fixpoint values stored in the ROM.