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| author | Jack | 2022-07-30 22:41:15 +0000 |
|---|---|---|
| committer | Jack | 2022-07-30 22:41:15 +0000 |
| commit | 4cd44fa4dab370fcc5c20bcacc1fa0ee02327252 (patch) | |
| tree | 05730be260feca0d2a870c4bb88325d36631a8fc /docs/src/explanations/interfaces-and-connections.md | |
| parent | fe9635ef21bad233945617a24ab16cfa4055f2d1 (diff) | |
| parent | bced77045c8fc5db37e40b159c49220929e15d46 (diff) | |
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'docs/src/explanations/interfaces-and-connections.md')
| -rw-r--r-- | docs/src/explanations/interfaces-and-connections.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/src/explanations/interfaces-and-connections.md b/docs/src/explanations/interfaces-and-connections.md index 0fb8bae8..5d9cfd3c 100644 --- a/docs/src/explanations/interfaces-and-connections.md +++ b/docs/src/explanations/interfaces-and-connections.md @@ -150,7 +150,7 @@ Below we can see the resulting error for this example: ```scala mdoc:crash ChiselStage.emitVerilog(new BlockWithTemporaryWires) ``` -For more details and information, see [Deep Dive into Connection Operators](connection-operators.md) +For more details and information, see [Deep Dive into Connection Operators](connection-operators) NOTE: When using `Chisel._` (compatibility mode) instead of `chisel3._`, the `:=` operator works in a bidirectional fashion similar to `<>`, but not exactly the same. |