Merge branch 'master' into 3.5-release

1 files changed, 19 insertions, 27 deletions

diff --git a/docs/src/explanations/dataview.md b/docs/src/explanations/dataview.md
index 2f229bfc..bb8dbdd1 100644
--- a/docs/src/explanations/dataview.md
+++ b/docs/src/explanations/dataview.md
@@ -10,7 +10,6 @@ _New in Chisel 3.5_
 
 ```scala mdoc:invisible
 import chisel3._
-import chisel3.stage.ChiselStage.emitVerilog
 ```
 
 ## Introduction
@@ -91,7 +90,7 @@ class MyModule extends RawModule {
 Of course, this would result in very different looking Verilog:
 
 ```scala mdoc:verilog
-emitVerilog(new MyModule {
+getVerilogString(new MyModule {
   override def desiredName = "MyModule"
   axi := DontCare // Just to generate Verilog in this stub
 })
@@ -147,7 +146,7 @@ class AXIStub extends RawModule {
 This will generate Verilog that matches the standard naming convention:
 
 ```scala mdoc:verilog
-emitVerilog(new AXIStub)
+getVerilogString(new AXIStub)
 ```
 
 Note that if both the _Target_ and the _View_ types are subtypes of `Data` (as they are in this example),
@@ -175,7 +174,7 @@ class ConnectionExample extends RawModule {
 This results in the corresponding fields being connected in the emitted Verilog:
 
 ```scala mdoc:verilog
-emitVerilog(new ConnectionExample)
+getVerilogString(new ConnectionExample)
 ```
 
 ## Other Use Cases
@@ -206,17 +205,6 @@ The issue, is that Chisel primitives like `Mux` and `:=` only operate on subtype
 Tuples (as members of the Scala standard library), are not subclasses of `Data`.
 `DataView` provides a mechanism to _view_ a `Tuple` as if it were a `Data`:
 
-<!-- TODO replace this with stdlib import -->
-
-```scala mdoc:invisible
-// ProductDataProduct
-implicit val productDataProduct: DataProduct[Product] = new DataProduct[Product] {
-  def dataIterator(a: Product, path: String): Iterator[(Data, String)] = {
-    a.productIterator.zipWithIndex.collect { case (d: Data, i) => d -> s"$path._$i" }
-  }
-}
-```
-
 ```scala mdoc
 // We need a type to represent the Tuple
 class HWTuple2[A <: Data, B <: Data](val _1: A, val _2: B) extends Bundle
@@ -259,16 +247,24 @@ class TupleExample extends RawModule {
 
 ```scala mdoc:invisible
 // Always emit Verilog to make sure it actually works
-emitVerilog(new TupleExample)
+getVerilogString(new TupleExample)
 ```
 
 Note that this example ignored `DataProduct` which is another required piece (see [the documentation
 about it below](#dataproduct)).
 
-All of this is slated to be included the Chisel standard library.
+All of this is available to users via a single import:
+```scala mdoc:reset
+import chisel3.experimental.conversions._
+```
 
 ## Totality and PartialDataView
 
+```scala mdoc:reset:invisible
+import chisel3._
+import chisel3.experimental.dataview._
+```
+
 A `DataView` is _total_ if all fields of the _Target_ type and all fields of the _View_ type are 
 included in the mapping.
 Chisel will error if a field is accidentally left out from a `DataView`.
@@ -285,7 +281,6 @@ class BundleB extends Bundle {
 ```
 
 ```scala mdoc:crash
-{ // Using an extra scope here to avoid a bug in mdoc (documentation generation)
 // We forgot BundleA.foo in the mapping!
 implicit val myView = DataView[BundleA, BundleB](_ => new BundleB, _.bar -> _.fizz)
 class BadMapping extends Module {
@@ -294,8 +289,7 @@ class BadMapping extends Module {
    out := in.viewAs[BundleB]
 }
 // We must run Chisel to see the error
-emitVerilog(new BadMapping)
-}
+getVerilogString(new BadMapping)
 ```
 
 As that error suggests, if we *want* the view to be non-total, we can use a `PartialDataView`:
@@ -311,7 +305,7 @@ class PartialDataViewModule extends Module {
 ```
 
 ```scala mdoc:verilog
-emitVerilog(new PartialDataViewModule)
+getVerilogString(new PartialDataViewModule)
 ```
 
 While `PartialDataViews` need not be total for the _Target_, both `PartialDataViews` and `DataViews`
@@ -321,7 +315,6 @@ This has the consequence that `PartialDataViews` are **not** invertible in the s
 For example:
 
 ```scala mdoc:crash
-{ // Using an extra scope here to avoid a bug in mdoc (documentation generation)
 implicit val myView2 = myView.invert(_ => new BundleA)
 class PartialDataViewModule2 extends Module {
    val in = IO(Input(new BundleA))
@@ -330,8 +323,7 @@ class PartialDataViewModule2 extends Module {
    out.viewAs[BundleA] := in
 }
 // We must run Chisel to see the error
-emitVerilog(new PartialDataViewModule2)
-}
+getVerilogString(new PartialDataViewModule2)
 ```
 
 As noted, the mapping must **always** be total for the `View`.
@@ -394,7 +386,7 @@ resolution error.
 
 
 This section draws heavily from [[1]](https://stackoverflow.com/a/5598107/2483329) and
-[[2]](https://stackoverflow.com/a/5598107/2483329).
+[[2]](https://stackoverflow.com/a/8694558/2483329).
 In particular, see [1] for examples.
 
 #### Implicit Resolution Example
@@ -444,7 +436,7 @@ class FooToBar extends Module {
 ```
 
 ```scala mdoc:verilog
-emitVerilog(new FooToBar)
+getVerilogString(new FooToBar)
 ```
 
 However, it's possible that some user of `Foo` and `Bar` wants different behavior,
@@ -464,7 +456,7 @@ class FooToBarSwizzled extends Module {
 ```
 
 ```scala mdoc:verilog
-emitVerilog(new FooToBarSwizzled)
+getVerilogString(new FooToBarSwizzled)
 ```
 
 ### DataProduct