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authormergify[bot]2022-03-03 18:07:58 +0000
committerGitHub2022-03-03 18:07:58 +0000
commit271095622835df7b0025eb9fd55a99de9082dea2 (patch)
treee4f73281eb27bb23a5c9c9c9cf7dbc47103f21a2 /docs/src/cookbooks/cookbook.md
parent4b8584b1d2c46c76b1540e265a84eeb247d684e4 (diff)
Add Verilog-chisel side by side Reference Page to Docs (#2323) (#2426)
Co-authored-by: Shola Ogunkelu @Shorla Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com> Completed as part of Outreachy Internship Dec 2021-March 2022. (cherry picked from commit 362702f3fd79bf1071db4acecc679f25a0b94a8a) Co-authored-by: Olushola Ogunkelu <77856859+Shorla@users.noreply.github.com>
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@@ -31,7 +31,8 @@ Please note that these examples make use of [Chisel's scala-style printing](../e
* [How can I dynamically set/parametrize the name of a module?](#how-can-i-dynamically-setparametrize-the-name-of-a-module)
* Directionality
* [How do I strip directions from a bidirectional Bundle (or other Data)?](#how-do-i-strip-directions-from-a-bidirectional-bundle-or-other-data)
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+ * [Side-by-Side Comparison of Verilog to Chisel](verilog-vs-chisel.md)
+
## Type Conversions
### How do I create a UInt from an instance of a Bundle?