diff options
| author | Jack Koenig | 2021-09-17 21:01:26 -0700 |
|---|---|---|
| committer | Jack Koenig | 2021-09-17 21:01:26 -0700 |
| commit | 5c8c19345e6711279594cf1f9ddab33623c8eba7 (patch) | |
| tree | d9d6ced3934aa4a8be3dec19ddcefe50a7a93d5a /docs-target/src | |
| parent | e63b9667d89768e0ec6dc8a9153335cb48a213a7 (diff) | |
| parent | 958904cb2f2f65d02b2ab3ec6d9ec2e06d04e482 (diff) | |
Merge branch 'master' into 3.5-release
Diffstat (limited to 'docs-target/src')
| -rw-r--r-- | docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala index a76e412a..f41fff73 100644 --- a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala +++ b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala @@ -27,7 +27,7 @@ class VerilogMdocModifier extends PostModifier { case (None, _) => None } result match { - case Some(content) => s"```verilog\n$content```" + case Some(content) => s"```verilog\n$content```\n" case None => "" } } |
