Fix ChiselEnum docs (#2016)

Also add newline to end of `verilog` modifier code blocks so that there
is always a newline between code blocks and following material.

1 files changed, 1 insertions, 1 deletions

diff --git a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
index a76e412a..f41fff73 100644
--- a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
+++ b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
@@ -27,7 +27,7 @@ class VerilogMdocModifier extends PostModifier {
         case (None, _) => None
       }
     result match {
-      case Some(content) => s"```verilog\n$content```"
+      case Some(content) => s"```verilog\n$content```\n"
       case None          => ""
     }
   }