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authorJack Koenig2017-12-20 15:54:25 -0800
committerGitHub2017-12-20 15:54:25 -0800
commite27657118ff5915b96f8e3a467d464245fe09769 (patch)
tree2353d94bc70fa006639bf5019bde366b15e82b29 /coreMacros/src
parent0f5ba51572b22ff5c85f9dd1add82680e0620797 (diff)
Add compileOptions to Module.apply, use for invalidating submod ports (#747)
Fixes #746 Also add test for https://github.com/freechipsproject/firrtl/issues/705
Diffstat (limited to 'coreMacros/src')
-rw-r--r--coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 47c77c98..9f3ac88d 100644
--- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -38,7 +38,7 @@ class UIntTransform(val c: Context) extends SourceInfoTransformMacro {
class InstTransform(val c: Context) extends SourceInfoTransformMacro {
import c.universe._
def apply[T: c.WeakTypeTag](bc: c.Tree): c.Tree = {
- q"$thisObj.do_apply($bc)($implicitSourceInfo)"
+ q"$thisObj.do_apply($bc)($implicitSourceInfo, $implicitCompileOptions)"
}
}