summaryrefslogtreecommitdiff
path: root/coreMacros/src
diff options
context:
space:
mode:
authorJim Lawson2016-07-06 09:31:47 -0700
committerJim Lawson2016-07-18 15:49:45 -0700
commit12810b5efe6a8f872fbc1c63cdfb835ca354624f (patch)
tree1fe4d0666e28f15880bbaf164592bd2bba1eff7c /coreMacros/src
parentc5f9ea3133ef363ff8944e17d94fea79767b6bed (diff)
Update Chisel -> chisel3 references.
Diffstat (limited to 'coreMacros/src')
-rw-r--r--coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 82ad5b9e..ba14b78f 100644
--- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -3,7 +3,7 @@
// This file transform macro definitions to explicitly add implicit source info to Chisel method
// calls.
-package Chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
import scala.language.experimental.macros
import scala.reflect.macros.blackbox.Context
@@ -23,7 +23,7 @@ trait SourceInfoTransformMacro {
val c: Context
import c.universe._
def thisObj = c.prefix.tree
- def implicitSourceInfo = q"implicitly[_root_.Chisel.internal.sourceinfo.SourceInfo]"
+ def implicitSourceInfo = q"implicitly[_root_.chisel3.internal.sourceinfo.SourceInfo]"
}
class WireTransform(val c: Context) extends SourceInfoTransformMacro {